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| S25FL032P 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet (Preliminary) S25FL032P Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S25FL032P_00 Revision 02 Issue Date February 12, 2009 Data Sheet (Preliminary) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local sales office. 2 S25FL032P S25FL032P_00_02 February 12, 2009 S25FL032P 32-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet (Preliminary) Distinctive Characteristics Architectural Advantages Single power supply operation - Full voltage range: 2.7 to 3.6V read and write operations CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Process technology - Manufactured on 0.09 m MirrorBit(R) process technology Memory architecture - Uniform 64 KB sectors - Top or bottom parameter block (Two 64-KB sectors (top or bottom) broken down into sixteen 4-KB sub-sectors each) - 256-byte page size - Backward compatible with the S25FL032A device Package option - - - - - Industry Standard Pinouts 8-pin SO package (208 mils) 16-pin SO package (300 mils) 8-contact USON package (5 x 6 mm) 8-contact WSON package (6 x 8 mm) Program - - - - - - - - Page Program (up to 256 bytes) in 1.5 ms (typical) Program operations are on a page by page basis Accelerated programming mode via 9V W#/ACC pin Quad Page Programming Bulk erase function Sector erase (SE) command (D8h) for 64 KB sectors Sub-sector erase (P4E) command (20h) for 4 KB sectors Sub-sector erase (P8E) command (40h) for 8 KB sectors Performance Characteristics Speed - Normal READ (Serial): 40 MHz clock rate - FAST_READ (Serial): 104 MHz clock rate (maximum) - DUAL I/O FAST_READ: 80 MHz clock rate or 20 MB/s effective data rate - QUAD I/O FAST_READ: 80 MHz clock rate or 40 MB/s effective data rate Erase Cycling endurance - 100,000 cycles per sector typical Power saving standby mode - Standby Mode 80 A (typical) - Deep Power-Down Mode 3 A (typical) Data retention - 20 years typical Device ID - JEDEC standard two-byte electronic signature - RES command one-byte electronic signature for backward compatibility Memory Protection Features Memory protection - W#/ACC pin works in conjunction with Status Register Bits to protect specified memory areas - Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only One time programmable (OTP) area for permanent, secure identification; can be programmed and locked at the factory or by the customer Publication Number S25FL032P_00 Revision 02 Issue Date February 12, 2009 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. Data Sheet (Preliminary) General Description The S25FL032P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists of 64 uniform 64 KB sectors with the two (Top or Bottom) 64 KB sectors further split up into thirty-two 4KB sub sectors. The S25FL032P device is fully backward compatible with the S25FL032A device. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply. The S25FL032P device adds the following high-performance features using 5 new instructions: Dual Output Read using both SI and SO pins as output pins at a clock rate of up to 80 MHz Quad Output Read using SI, SO, W#/ACC and HOLD# pins as output pins at a clock rate of up to 80 MHz Dual I/O High Performance Read using both SI and SO pins as input and output pins at a clock rate of up to 80 MHz Quad I/O High Performance Read using SI, SO, W#/ACC and HOLD# pins as input and output pins at a clock rate of up to 80 MHz Quad Page Programming using SI, SO, W#/ACC and HOLD# pins as input pins to program data at a clock rate of up to 80 MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands. Each device requires only a 3.0-volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program operations. This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL032P device also offers a One-Time Programmable area (OTP) of up to 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions. 4 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2. 3. 4. 5. 6. 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Spansion SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Byte or Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Quad Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Dual and Quad I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Sector Erase / Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Monitoring Write Operations Using the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9 Data Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Hold Mode (HOLD#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 Accelerated Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 14 14 14 15 15 16 17 18 8. 9. Sector Address Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Dual Output Read Mode (DOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Quad Output Read Mode (QOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 DUAL I/O High Performance Read Mode (DIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 Quad I/O High Performance Read Mode (QIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 Read-ID (READ_ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.9 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10 Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.11 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.12 Read Configuration Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.13 Write Registers (WRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.14 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.15 QUAD Page Program (QPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.16 Parameter Sector Erase (P4E, P8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.17 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.18 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.19 Deep Power-Down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.20 Release from Deep Power-Down (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.21 Clear Status Register (CLSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.22 OTP Program (OTPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.23 Read OTP Data Bytes (OTPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Programming OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Reading OTP Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Locking OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 23 24 25 26 27 29 30 34 35 35 36 37 38 40 41 42 43 44 45 46 47 48 48 49 49 49 49 10. 11. 12. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 February 12, 2009 S25FL032P_00_02 S25FL032P 5 Data Sheet (Preliminary) 13. 14. 15. 16. 17. 18. 19. Program Acceleration via W#/ACC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18.1 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 SOC008 wide -- 8-pin Plastic Small Outline Package (208-mils Body Width) . . . . . . . . . . . 19.2 SO3 016 -- 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . 19.3 USON 8-contact (5 x 6 mm) No-Lead Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 WSON 8-contact (6 x 8 mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 60 61 62 20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Figures Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 6.1 Figure 6.2 Figure 7.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 9.16 Figure 9.17 Figure 9.18 Figure 9.19 Figure 9.20 Figure 9.21 Figure 9.22 Figure 9.23 Figure 9.24 Figure 9.25 Figure 9.26 Figure 9.27 Figure 10.1 Figure 10.2 Figure 11.1 Figure 11.2 Figure 13.1 Figure 14.1 Figure 14.2 Figure 17.1 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8-contact USON (5 x 6 mm) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8-contact WSON Package (6 x 8 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Data Bytes (READ) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence . . . . . . . . . . . . . . . 24 Dual Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Quad Output Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DUAL I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Continuous Dual I/O High Performance Read Instruction Sequence . . . . . . . . . . . . . . . . . . 28 QUAD I/O High Performance Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Continuous QUAD I/O High Performance Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . 30 Read Identification (RDID) Command Sequence and Data-Out Sequence . . . . . . . . . . . . . 30 Read-ID (RDID) Command Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Write Enable (WREN) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Write Disable (WRDI) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read Status Register (RDSR) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Read Configuration Register (RCR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Write Registers (WRR) Instruction Sequence - 8 data bits . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write Registers (WRR) Instruction Sequence - 16 data bits . . . . . . . . . . . . . . . . . . . . . . . . . 39 Page Program (PP) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 QUAD Page Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Parameter Sector Erase (P4E, P8E) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 42 Sector Erase (SE) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Bulk Erase (BE) Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Deep Power-Down (DP) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Release from Deep Power-Down (RES) Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 46 Release from Deep Power-Down and RES Command Sequence . . . . . . . . . . . . . . . . . . . . 47 Clear Status Register (CLSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 OTP Program Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Read OTP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 OTP Memory Map - Part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 OTP Memory Map - Part 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Power-Up Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power-down and Voltage Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ACC Program Acceleration Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Write Protect Setup and Hold Timing during WRR when SRWD = 1 . . . . . . . . . . . . . . . . . . 58 February 12, 2009 S25FL032P_00_02 S25FL032P 7 Data Sheet (Preliminary) Tables Table 5.1 Table 7.1 Table 7.2 Table 7.3 Table 8.1 Table 8.2 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 9.6 Table 9.7 Table 9.8 Table 9.9 Table 11.1 Table 13.1 Table 15.1 Table 16.1 Table 17.1 S25FL032P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Configuration Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 TBPROT = 0 (Starts Protection from TOP of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 TBPROT=1 (Starts Protection from BOTTOM of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 S25FL032P Sector Address Table TBPARM=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 S25FL032P Sector Address Table TBPARM=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Manufacturer & Device ID - RDID (JEDEC 9Fh): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Product Group CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Product Group CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Product Group CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . .33 READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 S25FL032P Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 8 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 1. Block Diagram SRAM PS Array - L Logic X D E C Array - R RD DATA PATH IO HOLD# / IO3 SO / IO1 SCK W# / ACC / IO2 SI / IO0 CS# GND VCC SCK SI/IO0 DNC DNC DNC DNC GND W#/ACC/IO2 2. Connection Diagrams Figure 2.1 16-pin Plastic Small Outline Package (SO) HOLD#/IO3 VCC DNC DNC DNC DNC CS# SO/IO1 Note DNC = Do Not Connect (Reserved for future use) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 February 12, 2009 S25FL032P_00_02 S25FL032P 9 Data Sheet (Preliminary) Figure 2.2 8-pin Plastic Small Outline Package (SO) CS# SO/IO1 W#/ACC/IO2 GND 1 2 3 4 8 7 6 5 VCC HOLD#/IO3 SCK SI/IO0 Figure 2.3 8-contact USON (5 x 6 mm) Package CS# SO/IO1 W#/ACC/IO2 GND 1 2 WSON 8 7 6 5 VCC HOLD#/IO3 SCK SI/IO0 3 4 Figure 2.4 8-contact WSON Package (6 x 8 mm) CS# SO/IO1 W#/ACC/IO2 GND 1 2 WSON 8 7 6 5 VCC HOLD#/IO3 SCK SI/IO0 3 4 3. Input/Output Descriptions Signal SO/IO1 I/O I/O Description Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes. Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Functions as an output pin in Dual and Quad I/O mode. Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. Chip Select: Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Functions as an output pin in Quad I/O mode. Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Functions as an output pin in Quad I/O mode. Supply Voltage Ground SI/IO0 I/O SCK Input CS# Input HOLD#/IO3 I/O W#/ACC/IO2 VCC GND I/O Input Input 10 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 4. Logic Symbol VCC SI/IO0 SCK CS# W#/ACC/IO2 HOLD#/IO3 SO/IO1 GND February 12, 2009 S25FL032P_00_02 S25FL032P 11 Data Sheet (Preliminary) 5. Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 032 P 0X M F I 00 1 Packing Type (Note 1) 0 = Tray 1 = Tube 3 = 13" Tape and Reel Model Number (Additional Ordering Options) 01 = 8-pin SO package / 8-contact USON package 00 = 16-pin SO package / 8-contact WSON package Temperature Range I = Industrial (-40C to + 85C) Package Materials F = Lead (Pb)-free Package Type M = 8-pin / 16-pin SO package N = 8-contact USON / WSON package Speed 0X = 104 MHz Device Technology P = 0.09 m MirrorBit(R) Process Technology Density 032 = Device Family 32 Mbit S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory 5.1 Valid Combinations Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device. Table 5.1 S25FL032P Valid Combinations Table S25FL032P Valid Combinations Base Ordering Part Number S25FL032P Speed Option 0X Package & Temperature MFI NFI Model Number 00, 01 Packing Type 0, 1, 3 Package Marking FL032P + (Temp) + F Note 1. The last OPN character "x" signifies the Packing type. 12 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 6. Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes. When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes: SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0) SCK remains at 1 for (CPOL = 1, CPHA = 1 Mode 3) Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master SI SCK SCK SO SI SCK SO SI SCK SO SI SPI Memory Device CS3 CS2 CS1 CS# W#/ACC HOLD# SPI Memory Device SPI Memory Device CS# W#/ACC HOLD# CS# W#/ACC HOLD# Note The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. Figure 6.2 SPI Modes Supported CS# CPOL CPHA Mode 0 Mode 3 0 1 0 1 SCK SCK SI SO MSB MSB February 12, 2009 S25FL032P_00_02 S25FL032P 13 Data Sheet (Preliminary) 7. Device Operations All Spansion SPI devices accept and output data in bytes (8 bits at a time). 7.1 Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1 requires an erase operation. 7.2 Quad Page Programming The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using 4 pins as inputs at the same time, thus effectively quadrupling the data transfer rate, compared to the Page Program (PP) instruction. 7.3 Dual and Quad I/O Mode The S25FL032P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode and the Dual/Quad I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows data to be transferred to or from the device at two to four times the rate of standard SPI devices. When operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a time. 7.4 Sector Erase / Bulk Erase The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sectorwide (SE) or array-wide (BE) level. In addition to the 64-KB Sector Erase (SE), the S25FL032P device also offers 4-KB Parameter Sector Erase (P4E) and 8-KB Parameter Sector Erase (P8E). 7.5 Monitoring Write Operations Using the Status Register The host system can determine when a Write Register, program, or erase operation is complete by monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL032P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure. 7.6 Active Power and Standby Power Modes The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but may still be in the Active Power mode until all program, erase, and Write Registers operations have completed. The device then goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power-Down (DP) command provides additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or erase commands, and reduces its power consumption to IDP. 14 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 7.7 Status Register The Status Register contains the status and control bits that can be read or set by specific commands (see Table 9.1 on page 22). These bits configure different protection configurations and supply information of operation of the device. (for details see Table 9.8, S25FL032P Status Register on page 36): Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase operation. Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch. Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected against program and erase commands. Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check. Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check. Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit is set to 1 and the W#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. 7.8 Configuration Register The Configuration Register contains the control bits that can be read or set by specific commands. These bits configure different configurations and security features of the device. The FREEZE bit locks the BP2-0 bits in Status Register and the TBPROT and TBPARM bits in the Configuration Register. Note that once the FREEZE bit has been set to `1', then it cannot be cleared to `0' until a power-on-reset is executed. As long as the FREEZE bit is set to `0', then the other bits of the Configuration Register, including FREEZE bit, can be written to. The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is, W#/ACC becomes IO2 and HOLD# becomes IO3. The instructions for Serial, Dual Output, and Dual I/O reads will function as normal. The W#/ACC and HOLD# functionality will not work when the device is set in Quad mode. The TBPARM bit defines the logical location of the 4 KB parameter sectors. The parameter sectors consist of thirty two 4 KB sectors. All sectors other than the parameter sectors are defined to be 64-KB uniform in size. When TBPARM is set to a `1', the 4 KB parameter sectors starts at the top of the array. When TBPARM is set to a `0', the 4 KB parameter sectors starts at the bottom of the array. Note that once this bit is set to a '1', it cannot be changed back to '0'. The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile. When BPNV is set to a `1', the BP2-0 bits in the Status Register are volatile and will be reset to binary 111 after power on reset. When BPNV is set to a `0', the BP2-0 bits in the Status Register are non-volatile. Note that once this bit is set to a '1', it cannot be changed back to '0'. The TBPROT bit defines the operation of the block protection bits BP2, BP1, and BP0 in the Status Register. When TBPROT is set to a `0', then the block protection is defined to start from the top of the array. When TBPROT is set to a `1', then the block protection is defined to start from the bottom of the array. Note that once this bit is set to a '1', it cannot be changed back to '0'. Note: In case BPNV=1 (Volatile), the BP2-0 bits will always be considered as non-volatile. February 12, 2009 S25FL032P_00_02 S25FL032P 15 Data Sheet (Preliminary) Table 7.1 Configuration Register Table Bit 7 6 5 4 3 2 1 0 Bit Name NA NA TBPROT NA BPNV TBPARM QUAD FREEZE Configures start of block protection Configures BP2-0 bits in the Status Register Configures Parameter sector location Puts the device into Quad I/O mode Locks BP2-0 bits in the Status Register Bit Function Not Used Not Used 1 = Bottom Array (low address) 0 = Top Array (high address) (Default) Not Used 1 = Volatile 0 = Non-volatile (Default) 1 = Top Array (high address) 0 = Bottom Array (low address) (Default) 1 = Quad I/O 0 = Dual or Serial I/O (Default) 1 = Enabled 0 = Disabled (Default) Description Note (Default) indicates the value of each Configuration Register bit set upon initial factory shipment. 7.9 Data Protection Modes Spansion SPI Flash memory devices provide the following data protection methods: The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: - Page Program (PP) - Sector Erase (SE) - Bulk Erase (BE) - Write Disable (WRDI) - Write Register (WRR) - Parameter 4 KB Sector Erase (P4E) - Parameter 8 KB Sector Erase (P8E) - Quad Page Programming (QPP) - OTP Byte Programming (OTPP) Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not programmed or erased. Table 7.2 and Table 7.3 shows the sizes and address ranges of protected areas that are defined by Status Register bits BP2:BP0. Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write Disable (SRWD) bit together provide write protection. Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of a clock pulse count that is a multiple of eight before executing them. 16 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Table 7.2 TBPROT = 0 (Starts Protection from TOP of Array) Status Register Block Protected Address Range None 3F0000h-3FFFFFh 3E0000h-3FFFFFh 3C0000h-3FFFFFh 380000h-3FFFFFh 300000h-3FFFFFh 200000h-3FFFFFh 000000h-3FFFFFh Memory Array Protected Sectors 0 (1) SA63 (2) SA63:SA62 (4) SA63:SA60 (8) SA63:SA56 (16) SA63:SA48 (32) SA63:SA32 (64) SA63:SA0 Unprotected Address Range 000000h-3FFFFFh 000000h-3EFFFFh 000000h-3DFFFFh 000000h-3BFFFFh 000000h-37FFFFh 000000h-2FFFFFh 000000h-1FFFFFh None Unprotected Sectors SA63:SA0 SA62:SA0 SA61:SA0 SA59:SA0 SA55:SA0 SA47:SA0 SA31:SA0 None Protected Portion of Total Memory Area 0 1/64 1/32 1/16 1/8 1/4 1/2 All BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 Table 7.3 TBPROT=1 (Starts Protection from BOTTOM of Array) Status Register Block Protected Address Range None 000000h-00FFFFh 000000h-01FFFFh 000000h-03FFFFh 000000h-07FFFFh 000000h-0FFFFFh 000000h-1FFFFFh 000000h-3FFFFFh Memory Array Protected Sectors 0 (1) SA0 (2) SA0:SA1 (4) SA0:SA3 (8) SA0:SA7 (16) SA0:SA15 (32) SA0:SA31 (64) SA0:SA63 Unprotected Address Range 000000h-3FFFFFh 010000h-3FFFFFh 020000h-3FFFFFh 040000h-3FFFFFh 080000h-3FFFFFh 100000h-3FFFFFh 200000h-3FFFFFh None Unprotected Sectors SA0:SA63 SA1:SA63 SA2:SA63 SA4:SA63 SA8:SA63 SA16:SA63 SA32:SA63 None Protected Portion of Total Memory Area 0 1/64 1/32 1/16 1/8 1/4 1/2 ALL BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 7.10 Hold Mode (HOLD#) The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write Registers, program or erase operation that is currently in progress. The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of SCK (non-standard use). The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (nonstandard use) See Figure 7.1. The SO output is high impedance, and the SI and SCK inputs are ignored (don't care) for the duration of the Hold mode. CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high, followed by driving CS# low. Note: The HOLD Mode feature is disabled during Quad I/O Mode. February 12, 2009 S25FL032P_00_02 S25FL032P 17 Data Sheet (Preliminary) Figure 7.1 Hold Mode Operation SCK HOLD# Hold Condition (standard use) Hold Condition (non-standard use) 7.11 Accelerated Programming Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device uses the higher voltage on the pin to reduce the time required for program operations. Removing VHH from the W#/ACC pin returns the device to normal operation. Note that the W#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the W#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 18 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 8. Sector Address Table The Sector Address tables show the size of the memory array, sectors, and pages. The device uses pages to cache the program data before the data is programmed into the memory array. Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from 0 to 1) on a sub-sector, sector- or device-wide basis using the P4E/P8E, SE or BE commands. Table 8.1 and Table 8.2 show the starting and ending address for each sector. The complete set of sectors comprises the memory array of the Flash device. Table 8.1 S25FL032P Sector Address Table TBPARM=0 Address range Sector Start address SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h 3A0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h End address 3FFFFFh 3EFFFFh 3DFFFFh 3CFFFFh 3BFFFFh 3AFFFFh 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh 2CFFFFh 2BFFFFh 2AFFFFh 29FFFFh 28FFFFh 27FFFFh 26FFFFh 25FFFFh 24FFFFh 23FFFFh 22FFFFh 21FFFFh 20FFFFh SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Start address 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h End address 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh SS31 SS30 SS29 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Address range Sector Start address 01F000h 01E000h 01D000h 01C000h 01B000h 01A000h 019000h 018000h 017000h 016000h 015000h 014000h 013000h 012000h 011000h 010000h 00F000h 00E000h 00D000h 00C000h 00B000h 00A000h 009000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h End address 01FFFFh 01EFFFh 01DFFFh 01CFFFh 01BFFFh 01AFFFh 019FFFh 018FFFh 017FFFh 016FFFh 015FFFh 014FFFh 013FFFh 012FFFh 011FFFh 010FFFh 00FFFFh 00EFFFh 00DFFFh 00CFFFh 00BFFFh 00AFFFh 009FFFh 008FFFh 007FFFh 006FFFh 005FFFh 004FFFh 003FFFh 002FFFh 001FFFh 000FFFh Address range Note Sector SA0 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA1 is split up into sub-sectors SS16 - SS31(light gray shading) February 12, 2009 S25FL032P_00_02 S25FL032P 19 Data Sheet (Preliminary) Table 8.2 S25FL032P Sector Address Table TBPARM=1 Address Range Sector Start Address SS31 SS30 SS29 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 3FF000h 3FE000h 3FD000h 3FC000h 3FB000h 3FA000h 3F9000h 3F8000h 3F7000h 3F6000h 3F5000h 3F4000h 3F3000h 3F2000h 3F1000h 3F0000h 3EF000h 3EE000h 3ED000h 3EC000h 3EB000h 3EA000h 3E9000h 3E8000h 3E7000h 3E6000h 3E5000h 3E4000h 3E3000h 3E2000h 3E1000h 3E0000h End Address 3FFFFFh 3FEFFFh 3FDFFFh 3FCFFFh 3FBFFFh 3FAFFFh 3F9FFFh 3F8FFFh 3F7FFFh 3F6FFFh 3F5FFFh 3F4FFFh 3F3FFFh 3F2FFFh 3F1FFFh 3F0FFFh 3EFFFFh 3EEFFFh 3EDFFFh 3ECFFFh 3EBFFFh 3EAFFFh 3E9FFFh 3E8FFFh 3E7FFFh 3E6FFFh 3E5FFFh 3E4FFFh 3E3FFFh 3E2FFFh 3E1FFFh 3E0FFFh SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 SA34 SA33 SA32 Sector Start Address 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h 3A0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h End Address 3FFFFFh 3EFFFFh 3DFFFFh 3CFFFFh 3BFFFFh 3AFFFFh 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh 2CFFFFh 2BFFFFh 2AFFFFh 29FFFFh 28FFFFh 27FFFFh 26FFFFh 25FFFFh 24FFFFh 23FFFFh 22FFFFh 21FFFFh 20FFFFh SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Address Range Sector Start Address 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h End Address 1FFFFFh 1EFFFFh 1DFFFFh 1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh Address Range Note Sector SA62 is split up into sub-sectors SS0 - SS15 (dark gray shading) Sector SA63 is split up into sub-sectors SS16 - SS31 (light gray shading) 20 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9. Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on the rising edge of SCK. Table 9.1 lists the complete set of commands. Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written. The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR), Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read (QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read OTP Data (OTPR), Read Manufacturer and Device ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down and Read Electronic Signature (RES) command sequences are followed by a data output sequence on SO. CS# can be driven high after any bit of the sequence is output to terminate the operation. The Page Program (PP), Quad Page Program (QPP), 64 KB Sector Erase (SE), 4 KB Parameter Sector Erase (P4E), 8 KB Parameter Sector Erase (P8E), Bulk Erase (BE), Write Status and Configuration Registers (WRR), Program OTP space (OTPP), Write Enable (WREN), or Write Disable (WRDI) commands require that CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an exact multiple of eight. The device ignores any attempt to access the memory array during a Write Registers, program, or erase operation, and continues the operation uninterrupted. The instruction set is listed in Table 9.1. February 12, 2009 S25FL032P_00_02 S25FL032P 21 Data Sheet (Preliminary) Table 9.1 Instruction Set Operation Command READ FAST_READ DOR QOR Read DIOR QIOR RDID READ_ID WREN Write Control WRDI P4E P8E Erase SE BE PP Program QPP RDSR Status & Configuration Register WRR RCR CLSR DP Power Saving RES (ABh) 1010 1011 OTPP OTP OTPR (4Bh) 0100 1011 Read data in the OTP memory space 3 0 1 (42h) 0100 0010 (32h) 0011 0010 (05h) 0000 0101 (01h) 0000 0001 (35h) 0011 0101 (30h) 0011 0000 (B9h) 1011 1001 (ABh) 1010 1011 Quad Page Programming Read Status Register Write (Status & Configuration) Register Read Configuration Register (CFG) Reset the Erase and Program Fall Flag (SRS and SR6) and restore normal operation) Deep Power-Down Release from Deep Power-Down Mode Release from Deep Power-Down and Read Electronic Signature Program one byte of data in OTP memory space 3 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 to 256 1 to 1 to 2 1 to 1 0 0 1 to 1 1 to (04h) 0000 0100 (20h) 0010 0000 (40h) 0100 0000 (D8h) 1101 1000 (60h) 0110 0000 or (C7h) 1100 0111 (02h) 0000 0010 Write Disable 4 KB Parameter Sector Erase 8 KB (two 4KB) Parameter Sector Erase 64KB Sector Erase Bulk Erase Page Programming 0 3 3 3 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 to 256 (BBh) 1011 1011 (EBh) 1110 1111 (9Fh) 1001 1111 (90h) 1001 0000 (06h) 0000 0110 Dual I/O High Performance Read Quad I/O High Performance Read Read Identification Read Manufacturer and Device Identification Write Enable 3 3 0 3 0 1 1 0 0 0 0 2 0 0 0 One byte Command Code (03h) 0000 0011 (0Bh) 0000 1011 (3Bh) 0011 1011 (6Bh) 0110 1011 Read Data bytes Read Data bytes at Fast Speed Dual Output Read Quad Output Read Description Address Byte Cycle 3 3 3 3 Mode Bit Cycle 0 0 0 0 Dummy Byte Cycle 0 1 1 1 Data Byte Cycle 1 to 1 to 1 to 1 to 1 to 1 to 1 to 81 1 to 0 22 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.1 Read Data Bytes (READ) The Read Data Bytes (READ) command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 40 MHz. The host system must first select the device by driving CS# low. The READ command is then written to SI, followed by a 3 byte address (A23-A0). Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. Figure 9.1 and Table 9.1 on page 22 detail the READ command sequence. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single READ command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The READ command is terminated by driving CS# high at any time during data output. The device rejects any READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.1 Read Data Bytes (READ) Command Sequence CS# Mode 3 0 1 23 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Mode 0 Command 24 Bit Address SI 23 22 21 MSB 3210 Data Out 1 Data Out 2 SO Hi-Z 765432 MSB 107 February 12, 2009 S25FL032P_00_02 S25FL032P 23 Data Sheet (Preliminary) 9.2 Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command reads data from the memory array at the frequency (fSCK) presented at the SCK input, with a maximum speed of 104 MHz. The host system must first select the device by driving CS# low. The FAST_READ command is then written to SI, followed by a 3 byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. The memory array data, at that address, are output serially on SO at a frequency fSCK, on the falling edge of SCK. The FAST_READ command sequence is shown in Figure 9.2 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single FAST_READ command. When the highest address is reached, the address counter reverts to 000000h, allowing the read sequence to continue indefinitely. The FAST_READ command is terminated by driving CS# high at any time during data output. The device rejects any FAST_READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence CS# Mode 3 0 1 2 5 6 7 8 9 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 3 4 10 47 SCK Mode 0 Command SI SO Hi-Z 24 Bit Address 23 22 21 3 2 1 0 7 Dummy Byte 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB DATA OUT 2 DATA OUT 1 24 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.3 Dual Output Read Mode (DOR) The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction. The host system must first select the device by driving CS# low. The Dual Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the IO0 (SI) & IO1 (SO) pins at a frequency fSCK on the falling edge of SCK. The Dual Output Read command sequence is shown in Figure 9.3 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Dual Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The Dual Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Dual Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.3 Dual Output Read Instruction Sequence CS# 0 SCK Instruction SI/IO0 Hi-Z SO/IO1 23 22 21 * 24 Bit Address 3 2 1 0 7 * 7 * 5 3 1 7 * 5 3 1 7 6 Dummy Byte 5 4 3 2 1 0 6 SI Switches from Input to Output 4 2 0 6 4 2 0 6 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Byte 1 Byte 2 *MSB February 12, 2009 S25FL032P_00_02 S25FL032P 25 Data Sheet (Preliminary) 9.4 Quad Output Read Mode (QOR) The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction. The host system must first select the device by driving CS# low. The Quad Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency fSCK on the falling edge of SCK. The Quad Output Read command sequence is shown in Figure 9.4 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Quad Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The Quad Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Quad Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the S25FL device. Figure 9.4 Quad Output Read Instruction Sequence CS# 0 SCK Instruction SI/IO0 SO/IO1 W#/ACC/IO2 Hi-Z Hi-Z 24 Bit Address 23 22 21 * 321 0 Dummy Byte 765 43 210 * SI Switches from Input to Output 40 5 6 7 40 1 40 5 1 2 3 40 5 6 1 2 4 5 6 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 15 2 3 6 7 26 37 HOLD#/IO3 Hi-Z 7 3 7 * * * * * DATA DATA DATA DATA OUT 1 OUT 2 OUT 3 OUT 4 *MSB 26 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.5 DUAL I/O High Performance Read Mode (DIOR) The Dual I/O High Performance Read instruction is similar to the Dual Output Read instruction, except that it improves throughput by allowing input of the address bits (A23-A0) using 2 bits per SCK via two input pins (SI/IO2 and SO/IO1), at a maximum frequency of 80 MHz. The host system must first select the device by driving CS# low. The Dual I/O High Performance Read command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with two bits latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through IO0 (SI) and IO1 (SO). The DUAL I/O High Performance Read command sequence is shown in Figure 9.5 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single DUAL I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. In addition, address jumps can be done without exiting the Dual I/O High Performance Mode through the setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.5). This added feature removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O High Performance instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T CARE ("x"). If the Mode bits equal Axh, then the device remains in Dual I/O High Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the BBh instruction opcode, as shown in Figure 9.6, thus eliminating eight cycles for the instruction sequence. However, if the Mode bits are any value other than Axh, then the next instruction (after CS# is raised high and then asserted low) requires the instruction sequence, which is normal operation. The following sequences will release the device from Dual I/O High Performance Read mode; after which, the device can accept standard SPI instructions: 1. During the Dual I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised high and then asserted low, the device will be released from Dual I/O High Performance Read mode. 2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 & IO1) are not set for a valid instruction sequence, then the device will be released from Dual I/O High Performance Read mode. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be driven high at any time during data output to terminate a read operation. Figure 9.5 DUAL I/O High Performance Read Instruction Sequence CS# 0 SCK Instruction 24 Bit Address 22 20 2 0 6 4 2 0 6 4 1 2 3 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IO0 & IO1 Switches from Input to Output 2 0 6 4 2 0 6 SI/IO0 Hi-Z SO/IO1 23 21 * 3 1 7 * 5 3 1 7 * 5 3 1 7 * 5 3 1 7 * Mode Bits Byte 1 Byte 2 *MSB February 12, 2009 S25FL032P_00_02 S25FL032P 27 Data Sheet (Preliminary) Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence CS# 0 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK 24 Bit Address IO0 & IO1 Switches from Input to Output SI/IO0 SO/IO1 22 20 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 23 * 21 3 1 7 * 5 3 1 7 * 5 3 1 7 * 5 3 1 7 * *MSB Mode Bits Byte 1 Byte 2 28 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.6 Quad I/O High Performance Read Mode (QIOR) The Quad I/O High Performance Read instruction is similar to the Quad Output Read instruction, except that it further improves throughput by allowing input of the address bits (A23-A0) using 4 bits per SCK via four input pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3), at a maximum frequency of 80 MHz. The host system must first select the device by driving CS# low. The Quad I/O High Performance Read command is then written to SI, followed by a 3-byte address (A23-A0) and a 1-byte Mode instruction, with four bits latched on the rising edge of SCK. Note that four dummy clocks are required prior to the data input. Then the memory contents, at the address that is given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#). The Quad I/O High Performance Read command sequence is shown in Figure 9.7 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Quad I/O High Performance Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. In addition, address jumps can be done without exiting the Quad I/O High Performance Mode through the setting of the Mode bits (after the Address (A23-0) sequence, as shown in Figure 9.7). This added feature the removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Quad I/O High Performance instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the Mode bits are DON'T CARE ("x"). If the Mode bits equal Axh, then the device remains in Quad I/O High Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the EBh instruction opcode, as shown in Figure 9.8, thus eliminating eight cycles for the instruction sequence. The following sequences will release the device from Quad I/O High Performance Read mode; after which, the device can accept standard SPI instructions: 1. During the Quad I/O High Performance Instruction Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised high and then asserted low the device will be released from Quad I/O High Performance Read mode. 2. Furthermore, during any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0, IO1, IO2, & IO3) are not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance Read mode. It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock. The read instruction can be terminated by driving the CS# pin to the logic high state. The CS# pin can be driven high at any time during data output to terminate a read operation. Figure 9.7 QUAD I/O High Performance Instruction Sequence CS# 0 SCK 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Instruction 24 Bit Address 20 16 0 1 2 3 4 5 6 7 * Mode Bits DUMMY DUMMY 0 1 2 3 4 5 6 7 * Byte 1 0 1 2 3 IO's Switches from Input to Output 4 5 6 7 * Byte 2 0 1 2 3 4 5 6 7 * SI/IO0 Hi-Z SO/IO1 Hi-Z W#/ACC/IO2 HOLD#/IO3 Hi-Z 21 17 22 18 23 19 * *MSB February 12, 2009 S25FL032P_00_02 S25FL032P 29 Data Sheet (Preliminary) Figure 9.8 Continuous QUAD I/O High Performance Instruction Sequence CS# 0 SCK 24 Bit Address 20 21 22 23 * 16 17 18 19 IO's Switches from Input to Output 1 4 5 6 7 8 9 10 11 12 13 14 15 16 SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 0 1 2 3 4 5 6 7 0 1 2 3 DUMMY 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 * * Mode Bits DUMMY * Byte 1 * Byte 2 *MSB 9.7 Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. The manufacturer identification is assigned by JEDEC; for Spansion devices, it is 01h. The device identification (2 bytes) and CFI bytes are assigned by the device manufacturer. See Table 9.2 on page 31 for device ID data. The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backwardcompatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. The system can read CFI information at the addresses given in Table 9.3. The host system must first select the device by driving CS# low. The RDID command is then written to SI, and each bit is latched on the rising edge of SCK. The 3-byte device identification data is output from the memory array on SO at a frequency fSCK, on the falling edge of SCK. The RDID command sequence is shown in Figure 9.9 and Table 9.1 on page 22. Driving CS# high after the device identification data has been read at least once terminates the RDID command. Driving CS# high at any time during data output (for example, while reading the extended CFI bytes), also terminates the RDID operation. The device rejects any RDID command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.9 Read Identification (RDID) Command Sequence and Data-Out Sequence CS# SCK Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 Mode 0 Command SI Manufacturer Identification SO Hi-Z MSB Device Identification 15 14 13 3 2 1 0 30 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh): Device Manuf. ID Byte 0 S25FL032P SPI Flash Notes 1. Byte 0 is Manufacturer ID of Spansion. 2. Byte 1 & 2 is Device Id. 3. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow. 4. Bytes 4, 5 and 6 are Spansion reserved (do not use). 5. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF. 6. Bytes 10h-50h are factory programmed per JEDEC standard. 01h Byte 1 02h Device Id Byte 2 15h # Extended bytes Byte 3 4Dh Table 9.3 Product Group CFI Query Identification String Byte 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 51h 52h 59h 02h 00h 40h 00h 00h 00h 00h 00h Primary OEM Command Set Query Unique ASCII string "QRY" Description Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Table 9.4 Product Group CFI System Interface String Byte 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 27h 36h 00h 00h 0Bh 0Bh 09h 0Fh 01h 01h 02h 01h Description VCC Min. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) VCC Max. (erase/program): (D7-D4: Volt, D3-D0: 100 mV) VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte program 2N s Typical timeout for Min. size Page program 2N s (00h = not supported) Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte program 2N times typical Max. timeout for page program 2N times typical Max. timeout per individual sector erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) February 12, 2009 S25FL032P_00_02 S25FL032P 31 Data Sheet (Preliminary) Table 9.5 Product Group CFI Device Geometry Definition Byte 27h 28h Data 16h 05h Device Size = 2 N byte; Flash Device Interface Description; 00h = x8 only 01h = x16 only 29h 00h 02h = x8/x16 capable 03h = x32 only 04h = Single I/O SPI, 3-byte address 05h = Multi I/O SPI, 3-byte address 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 08h 00h 02h 1Fh 00h Erase Block Region 1 Information (refer to CFI publication 100) 10h 00h 3Dh 00h Erase Block Region 2 Information (refer to CFI publication 100) 00h 01h 00h 00h Erase Block Region 3 Information (refer to CFI publication 100) 00h 00h 00h 00h Erase Block Region 4 Information (refer to CFI publication 100) 00h 00h Max. number of bytes in multi-byte write = 2N (00 = not supported) Number of Erase Block Regions within device 1 = Uniform Device, 2 = Parameter Block Description 32 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Table 9.6 Product Group CFI Primary Vendor-Specific Extended Query Byte 40h 41h 42h 43h 44h Data 50h 52h 49h 31h 33h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 00b = Required, 01b = Not Required Process Technology (Bits 5-2) 0000b = 0.23 m Floating Gate 0001b = 0.17 m Floating Gate 0010b = 0.23 m MirrorBit 0010b = 0.20 m MirrorBit 0011b = 0.11 m Floating Gate 0100b = 0.11 m MirrorBit 0101b = 0.09 m MirrorBit 1000b = 0.065 m MirrorBit Erase Suspend 0 = Not Supported, 1 = Read Only, 2 = Read & Write Sector Protect 00 = Not Supported, X = Number of sectors in per smallest group Temporary Sector Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect Scheme 04 = High Voltage Method 05 = Software Command Locking Method 08 = Advanced Sector Protection Method Simultaneous Operation 00 = Not Supported, X = Number of Sectors outside Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 03 = 256 Byte Page ACC (Acceleration) Supply Minimum 00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV) ACC (Acceleration) Supply Maximum 00 = Not Supported, (D7-D4: Volt, D3-D0: 100 mV) W# Protection 07 = Uniform Device with Top or Bottom Write Protect (user select) Program Suspend 00 = Not Supported, 01 = Supported Query-unique ASCII string "PRI" Description 45h 15h 46h 47h 48h 00h 01h 00h 49h 05h 4Ah 4Bh 00h 01h 4Ch 03h 4Dh 4Eh 4Fh 50h 85h 95h 07h 00h Note CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information tables to obtain the VCC range for particular part numbers. Please consult the AC Characteristics on page 56 for typical timeout specifications. February 12, 2009 S25FL032P_00_02 S25FL032P 33 Data Sheet (Preliminary) 9.8 Read-ID (READ_ID) The READ_ID instruction provides the S25FL032P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code "90h" followed by a 24-bit address (which is either 00000h or 00001h). Following this, the Manufacturer ID and the Device ID are shifted out on the SO output pin starting after the falling edge of the SCK serial clock input signal. If the 24-bit address is set to 000000h, the Manufacturer ID is read out first followed by the Device ID. If the 24-bit address is set to 000001h, then the Device ID is read out first followed by the Manufacturer ID. The Manufacturer ID and the Device ID are always shifted out on the SO output pin with the MSB first, as shown in Figure 10-14. Once the device is in Read-ID mode, the Manufacturer ID and Device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on the CS# input pin. The maximum clock frequency for the Read-ID (90h) command is at 104 MHz (FAST_READ). The Manufacturer ID & Device ID is output continuously until terminated by a low to high transition on CS# chip select input pin. Figure 9.10 Read-ID (RDID) Command Timing Diagram CS# 0 SCK Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI 23 22 21 MSB 3 2 1 0 Manufacture Identification Device Identification High Impedance SO 7 6 5 4 3 2 1 0 Table 9.7 READ_ID Data-Out Sequence Address Manufacturer Identification Device Identification 00000h 00001h Uniform 01h 15h 34 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.9 Write Enable (WREN) The Write Enable (WREN) command (see Figure 9.11) sets the Write Enable Latch (WEL) bit to a 1, which enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase (SE or BE), Write Registers (WRR) and OTP Program (OTPP) command. The host system must first drive CS# low, write the WREN command, and then drive CS# high. Figure 9.11 Write Enable (WREN) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI Hi-Z SO 9.10 Write Disable (WRDI) The Write Disable (WRDI) command (see Figure 9.12) resets the Write Enable Latch (WEL) bit to a 0, which disables the device from accepting a Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase (SE, BE), Write Registers (WRR) and OTP Program (OTPP) command. The host system must first drive CS# low, write the WRDI command, and then drive CS# high. Any of following conditions resets the WEL bit: Power-up Write Disable (WRDI) command completion Write Registers (WRR) command completion Page Program (PP) command completion Quad Page Program (QPP) completion Parameter Sector Erase (P4E, P8E) completion Sector Erase (SE) command completion Bulk Erase (BE) command completion OTP Program (OTPP) completion Figure 9.12 Write Disable (WRDI) Command Sequence CS# Mode 3 01234567 SCK Mode 0 Command SI Hi-Z SO February 12, 2009 S25FL032P_00_02 S25FL032P 35 Data Sheet (Preliminary) 9.11 Read Status Register (RDSR) The Read Status Register (RDSR) command outputs the state of the Status Register bits. Table 9.8 shows the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, or Write Registers operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress. Figure 9.13 shows the RDSR command sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. Table 9.8 S25FL032P Status Register Bit 7 Status Register Bit SRWD Bit Function Status Register Write Disable Description 1 = Protects when W#/ACC is low 0 = No protection, even when W#/ACC is low 0 = No Error 1 = Error occurred 0 = No Error 1 = Error occurred 6 P_ERR Programming Error Occurred 5 4 3 2 1 E_ERR BP2 BP1 BP0 WEL Erase Error Occurred Block Protect Protects selected Block from Program or Erase Write Enable Latch 1 = Device accepts Write Registers, program or erase commands 0 = Ignores Write Registers, program or erase commands 1 = Device Busy a Write Registers, program or erase operation is in progress 0 = Ready. Device is in standby mode and can accept commands. 0 WIP Write in Progress Figure 9.13 Read Status Register (RDSR) Command Sequence CS# Mode 3 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Mode 0 Command SI SO Hi-Z 76543210765432107 MSB Status Register Out MSB Status Register Out The following describes the status and control bits of the Status Register. Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such operation is in progress. This bit is a Read-only bit. Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers, program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI command, and is also automatically reset to 0 after the completion of a Write Registers, program, or erase operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR command. Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile, depending on the state of the non-volatile bit BPNV in the Configuration register. The Block Protection (BP2, BP1, BP0) bits are written with the Write Registers (WRR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1's, the relevant memory area is protected against Page Program (PP), 36 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase (BE) instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0's. The default condition of the BP2-0 bits is binary 000 (all 0's). Erase Error bit (E_ERR): The Erase Error Bit is used as a Erase operation success and failure check. When the Erase Error bit is set to a "1", it indicates that there was an error which occurred in the last erase operation. With the Erase Error bit set to a "1", this bit is reset with the Clear Status Register (CLSR) command. Program Error bit (P_ERR): The Program Error Bit is used as a Program operation success and failure check. When the Program Error bit is set to a "1", it indicates that there was an error which occurred in the last program operation. With the Program Error bit set to a "1", this bit is reset with the Clear Status Register (CLSR) command. Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#/ACC) signal. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#/ACC) input pin. The Status Register Write Disable (SRWD) bit and the Write Protect (W#/ ACC) signal allow the device to be put in the Hardware Protected mode. With the Status Register Write Disable (SRWD) bit set to a "1" and the W#/ACC driven to the logic low state, the device enters the Hardware Protected mode; the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) and the nonvolatile bits of the Configuration Register (TBPARM, TBPROT, BPNV and QUAD) become read-only bits and the Write Registers (WRR) instruction opcode is no longer accepted for execution. 9.12 Read Configuration Register (RCR) The Read Configuration Register (RCR) instruction opcode allows the Configuration Register contents to be read out of the SO serial output pin. The Configuration Register contents may be read at any time, even while a program, erase, or write cycle is in progress. When one of these cycles is in progress, it is recommended to the user to check the Write In Progress (WIP) bit of the Status Register before issuing a new instruction opcode to the device. The Configuration Register originally shows 00h when the device is first shipped from the factory to the customer. Figure 9.14 Read Configuration Register (RCR) Instruction Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK In s t r u c t i o n SI Configuration Register Out Configuration Register Out 0 7 6 5 4 3 2 1 0 7 SO High Impedance 7 6 5 4 3 2 1 MSB MSB MSB February 12, 2009 S25FL032P_00_02 S25FL032P 37 Data Sheet (Preliminary) 9.13 Write Registers (WRR) The Write Registers (WRR) command allows changing the bits in the Status and Configuration Registers. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to writing the WRR command. Table 9.8 shows the status register bits and their functions. The host system must drive CS# low, then write the WRR command and the appropriate data byte on SI Figure 9.15. The WRR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. The Status Register consists of one data byte in length; similarly, the Configuration Register is also one data byte in length. The CS# pin must be driven to the logic low state during the entire duration of the sequence. The WRR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W#/ACC pin together place the device in the Hardware Protected Mode (HPM). The device ignores all WRR commands once it enters the Hardware Protected Mode (HPM). Table 9.9 shows that W#/ACC must be driven low and the SRWD bit must be 1 for this to occur. The Write Registers (WRR) instruction has no effect on the P/E Error and the WIP bits of the Status & Configuration Registers. Any bit reserved for the future is always read as a `0' The CS# chip select input pin must be driven to the logic high state after the eighth (see Figure 9.15) or sixteenth (see Figure 9.16) bit of data has been latched in. If not, the Write Registers (WRR) instruction is not executed. If CS# is driven high after the eighth cycle then only the Status Register is written to; otherwise, after the sixteenth cycle both the Status and Configuration Registers are written to. As soon as the CS# chip select input pin is driven to the logic high state, the self-timed Write Registers cycle is initiated. While the Write Registers cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is a `1' during the self-timed Write Registers cycle, and is a `0' when it is completed. When the Write Registers cycle is completed, the Write Enable Latch (WEL) is set to a `0'. The WRR command can operate at a maximum clock frequency of 104 MHz. Figure 9.15 Write Registers (WRR) Instruction Sequence - 8 data bits CS# 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 In st r u ct i o n St at u s Regi s t er In SI 7 MSB 6 5 4 3 2 1 0 SO High Impedance 38 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Figure 9.16 Write Registers (WRR) Instruction Sequence - 16 data bits S CS# 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction Status Register In Configuration Register In SI 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 SO High Impedance Table 9.9 Protection Modes W#/ ACC 1 1 0 SRWD Bit 1 0 0 Software Protected (SPM) Memory Content Mode Write Protection of Registers Status & Configuration Registers are Writable (if WREN instruction has set the WEL bit). The values in the SRWD, BP2, BP1, & BP0 bits & those in the Configuration Register can be changed Status & Configuration Registers are Hardware Write Protected. The values in the SRWD, BP2, BP1, & BP0 bits & those in the Configuration Register cannot be changed Protected Area Protected against Page Program, Quad Page Program, Parameter Sector Erase, Sector Erase, and Bulk Erase Protected against Page Program, Quad Input Program, Sector Erase, and Bulk Erase Unprotected Area Ready to accept Page Program, Quad Page Program, Parameter Sector Erase, & Sector Erase instructions Ready to accept Page Program, Quad Input Program & Sector Erase instructions 0 1 Hardware Protected (HPM) Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.2 on page 17. Table 9.9 shows that neither W#/ACC or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the SRWD bit after driving W#/ACC low, or by driving W#/ACC low after setting the SRWD bit. However, the device disables HPM only when W#/ACC is driven high. Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM). If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be used. The Status and Configuration registers originally default to 00h, when the device is first shipped from the factory to the customer. February 12, 2009 S25FL032P_00_02 S25FL032P 39 Data Sheet (Preliminary) 9.14 Page Program (PP) The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN command is required prior to writing the PP command. The host system must drive CS# low, and then write the PP command, three address bytes, and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are programmed from the starting address of the same page (from the address whose 8 least significant bits are all zero). CS# must be driven low for the entire duration of the PP sequence. The command sequence is shown in Figure 9.17 and Table 9.1 on page 22. The device programs only the last 256 data bytes sent to the device. If the 8 least significant address bits (A7A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are programmed from the starting address of the same page (from the address whose 8 least significant bits are all zero). If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effect on the other bytes in the same page. The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tPP. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (BP2:BP0) (see Table 7.2 on page 17). Figure 9.17 Page Program (PP) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Mode 0 Command 24 Bit Address 23 22 21 MSB 3 2 1 0 7 6 5 Data Byte 1 4 3 2 1 0 SI MSB 2072 2074 2075 2073 2076 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2077 2078 SCK Data Byte 2 Data Byte 3 1 0 7 6 5 4 3 2 1 0 7 MSB 6 Data Byte 256 5 4 3 2 1 0 SI 7 MSB 6 5 4 3 2 MSB 40 S25FL032P S25FL032P_00_02 February 12, 2009 2079 Data Sheet (Preliminary) 9.15 QUAD Page Program (QPP) The Quad Page Program instruction is similar to the Page Program instruction, except that the Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#), instead of just one pin (SI) as in the case of the Page Program (PP) instruction. This effectively increases the data transfer rate by up to four times, as compared to the Page Program (PP) instruction. The QPP feature can improve performance for PROM Programmer and applications that have slow clock speeds < 5 MHz. Systems with faster clock speed will not realize much benefit for the QPP instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use QPP, the Quad Enable Bit in the Configuration Register must be set (QUAD = 1). A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL = 1). The instruction is initiated by driving the CS# pin low then shifting the instruction code "32h" followed by a 24 bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown below. Figure 9.18 QUAD Page Program Instruction Sequence CS# 0 SCK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Instruction 24 Bit Address 23 22 * 21 3 2 1 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 * Byte 1 * Byte 2 * Byte 3 * Byte 4 CS# 536 537 538 539 540 541 542 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 4 5 6 0 1 2 4 5 6 0 1 2 4 5 6 0 1 2 * Byte 5 * Byte 6 * Byte 7 * Byte 8 * Byte 9 * Byte 10 * Byte 11 * Byte 12 3 3 7 3 7 3 7 * * * * Byte 253 Byte 254 Byte 255 Byte 256 543 *MSB February 12, 2009 S25FL032P_00_02 S25FL032P 41 Data Sheet (Preliminary) 9.16 Parameter Sector Erase (P4E, P8E) The Parameter Sector Erase (P4E, P8E) command sets all bits at all addresses within a specified sector to a logic 1 (FFh). A WREN command is required prior to writing the Parameter Sector Erase commands. The host system must drive CS# low, and then write the P4E or P8E command, plus three address bytes on SI. Any address within the sector (see Table 5.1 on page 12) is a valid address for the P4E or P8E command. CS# must be driven low for the entire duration of the P4E/P8E sequence. The command sequence is shown in Figure 9.19 and Table 9.1 on page 22. The host system must drive CS# high after the device has latched the 8th bit of the P4E/P8E command, otherwise the device does not execute the command. The parameter sector erase operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the parameter sector erase operation is in progress. The WIP bit is 1 during the P4E/P8E operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). A Parameter Sector Erase (P4E, P8E) instruction applied to a sector that has been Write Protected through the Block Protect Bits will not be executed. The Parameter Sector Erase Command (P8E) erases two of the 4 KB Sectors in selected address space. The Parameter Sector Erase Command (P8E) erases two sequential 4 KB Parameter Sectors in the selected address space. The address LSB is disregarded so that two sequential 4 KB Parameter Sectors are erased. The 24 Bit Address is any location within the first Sector to be erased (n), and the next sequential 4 KB Parameter Sector will also be erased (n+1). The 4 KB parameter Sector will only be erased properly if n or n+1 is a valid 4 KB parameter Sector. i.e. If n is not a valid 4K parameter Sector, then it will not be erased. If n+1 is not a valid 4 KB parameter Sector, then it will not be erased. Figure 9.19 Parameter Sector Erase (P4E, P8E) Instruction Sequence CS# 0 SCK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Instruction 24 Bit Address SI 20h or 40h 23 22 21 MSB 3 2 1 0 42 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.17 Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the SE command. The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any address within the sector (see Table 7.2 on page 17) is a valid address for the SE command. CS# must be driven low for the entire duration of the SE sequence. The command sequence is shown in Figure 9.20 and Table 9.1 on page 22. The host system must drive CS# high after the device has latched the 8th bit of the SE command, otherwise the device does not execute the command. The SE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tSE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a SE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.2 on page 17). Otherwise, the device ignores the command. Figure 9.20 Sector Erase (SE) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCK Mode 0 Command 24 bit Address 23 MSB SI Hi-Z 22 21 3 2 1 0 SO February 12, 2009 S25FL032P_00_02 S25FL032P 43 Data Sheet (Preliminary) 9.18 Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the BE command. The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the entire duration of the BE sequence. The command sequence is shown in Figure 9.21 and Table 9.1 on page 22. The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise the device does not execute the command. The BE operation begins as soon as CS# is driven high. The device internally controls the timing of the operation, which requires a period of tBE. The Status Register may be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.2 on page 17). Otherwise, the device ignores the command. Figure 9.21 Bulk Erase (BE) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI SO Hi-Z 44 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.19 Deep Power-Down (DP) The Deep Power-Down (DP) command provides the lowest power consumption mode of the device. It is intended for periods when the device is not in active use, and ignores all commands except for the Release from Deep Power-Down (RES) command. The DP mode therefore provides the maximum data protection against unintended write operations. The standard standby mode, which the device goes into automatically when CS# is high (and all operations in progress are complete), should generally be used for the lowest power consumption when the quickest return to device activity is required. The host system must drive CS# low, and then write the DP command on SI. CS# must be driven low for the entire duration of the DP sequence. The command sequence is shown in Figure 9.22 and Table 9.1 on page 22. The host system must drive CS# high after the device has latched the 8th bit of the DP command, otherwise the device does not execute the command. After a delay of tDP, the device enters the DP mode and current reduces from ISB to IDP (see Table 16.1 on page 55). Once the device has entered the DP mode, all commands are ignored except the RES command (which releases the device from the DP mode). The RES command also provides the Electronic Signature of the device to be output on SO, if desired (see Section 9.20 and 9.20.1). DP mode automatically terminates when power is removed, and the device always powers up in the standard standby mode. The device rejects any DP command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.22 Deep Power-Down (DP) Command Sequence CS# tDP Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command SI Hi-Z SO Standby Mode Deep Power-down Mode February 12, 2009 S25FL032P_00_02 S25FL032P 45 Data Sheet (Preliminary) 9.20 Release from Deep Power-Down (RES) The device requires the Release from Deep Power-Down (RES) command to exit the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands except RES are ignored. The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire duration of the sequence. The command sequence is shown in Figure 9.23 and Table 9.1 on page 22. The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions from DP mode to the standby mode after a delay of tRES (see Figure 18.1). In the standby mode, the device can execute any read or write command. Figure 9.23 Release from Deep Power-Down (RES) Command Sequence CS# Mode 3 0 1 2 3 4 5 6 7 SCK Mode 0 Command tRES SI Hi-Z SO Deep Power-down Mode Standby Mode 46 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 9.20.1 Release from Deep Power-Down and Read Electronic Signature (RES) The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.24 and Table 9.1 on page 22 for the command sequence and signature value. The Electronic Signature is not to be confused with the identification data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead. After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to output the Electronic Signature repeatedly. When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as previously described. The RES command always provides access to the Electronic Signature of the device and can be applied even if DP mode has not been entered. Any RES command issued while an erase, program, or Write Registers operation is in progress not executed, and the operation continues uninterrupted. Figure 9.24 Release from Deep Power-Down and RES Command Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Command 3 Dummy Bytes tRES 1 0 Electronic ID SI SO Hi-Z 23 22 21 MSB 3 2 7 MSB 6 5 4 3 2 1 0 Software Protect Mode Standby Mode 9.21 Clear Status Register (CLSR) The Clear Status Register command resets bit SR5 (Erase Fail Flag) and bit SR6 (Program Fail Flag). It is not necessary to set the WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be unchanged after this command is executed. This command also resets the State machine and loads latches Figure 9.25 Clear Status Register (CLSR) Instruction Sequence CS# S 0 SCK 1 2 3 4 5 6 7 Instruction SI February 12, 2009 S25FL032P_00_02 S25FL032P 47 Data Sheet (Preliminary) 9.22 OTP Program (OTPP) The OTP Program command programs data in the OTP region, which is in a different address space from the main array data. Refer to, "OTP Regions"for details on the OTP region. The protocol of the OTP Program command is the same as the Page Program command, except that the OTP Program command requires exactly one byte of data; otherwise, the command will be ignored. To program the OTP in bit granularity, the rest of the bits within the data byte can be set to "1". The OTP memory space can be programmed one or more times, provided that the OTP memory space is not locked (as described in "Locking OTP Regions"). Subsequent OTP programming can be performed only on the unprogrammed bits (that is, "1" data). Note: The Write Enable (WREN) command must precede the OTPP command before programming of the OTP can occur. Figure 9.26 OTP Program Instruction Sequence CS# 0 SCK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Instruction 24 Bit Address 23 22 21 MSB 3 2 1 0 7 MSB 6 Data Byte 1 SI 5 4 3 2 1 0 9.23 Read OTP Data Bytes (OTPR) The Read OTP Data Bytes command reads data from the OTP region. Refer to "OTP Regions" for details on the OTP region. The protocol of the Read OTP Data Bytes command is the same as the Fast Read Data Bytes command except that it will not wrap to the starting address after the OTP address is at its maximum; instead, the data will be indeterminate. Figure 9.27 Read OTP Instruction Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Instruction 24 Bit Address 23 22 21 3 2 1 0 7 6 Dummy Byte SI 5 4 3 2 1 0 DATA OUT 1 DATA OUT 2 1 0 7 MSB SO High Impedance 7 MSB 6 5 4 3 2 48 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 10. OTP Regions The OTP Regions are separately addressable from the main array and consists of two 8-byte (ESN), thirty 16-byte, and one 10-byte regions that can be individually locked. The two 8-byte regions enable permanent part identification through an Electronic Serial Number (ESN). The customer can utilize the ESN to pair a Flash device with the system CPU/ASIC to prevent system cloning. The Spansion factory programs and locks the lower 8-byte ESN with a 64-bit randomly generated, unique number. The upper 8-byte ESN is left blank for customer use or, if special ordered, Spansion can program (and lock) in a unique customer ID. The thirty 16-byte and one 10-byte OTP regions are open for the customer usage. The thirty 16-byte, one 10-byte, and upper 8-byte ESN OTP regions can be individually locked by the end user. Once locked, the data cannot changed. The locking process is permanent and cannot be undone. The following general conditions should be noted with respect to the OTP Regions: On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads outside of the OTP Regions will be ignored The OTP Region is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. The ACC function is not available when the Secured Silicon Sector is enabled. The two 8-byte ESN region is a special order part (please contact your local Spansion sales representative for further details); otherwise, these regions are programmed to all zeroes and locked prior to shipping from the Spansion factory. The thirty 16-byte and one 10-byte OTP regions are left open for customer usage, but special care of the OTP locking must be maintained, or else a malevolent user can permanently lock the OTP regions. This is not a concern, if the OTP regions are not used. 10.1 Programming OTP Address Space The protocol of the OTP Program command (42h) is the same as the Page Program command. Refer to Table 9.1 for the command description and protocol. The OTP Program command can be issued multiple times to any given OTP address, but this address space can never be erased. After a given OTP region is programmed, it can be locked to prevent further programming with the OTP lock bits (refer to Section 10.3). The valid address range for OTP Program is depicted in the figure below. OTP Program operations outside the valid OTP address range will be ignored. 10.2 Reading OTP Data The protocol of the OTP Read command (4Bh) is the same as that of the Fast Read command. Refer to Table 9.1 for the command description and protocol. The valid address range for OTP Reads is depicted in the figure below. OTP Read operations outside the valid OTP address range will yield indeterminate data. 10.3 Locking OTP Regions In order to permanently lock the ESN and OTP regions, individual bits at the specified addresses can be set to lock specific regions of OTP memory, as highlighted in Figures 10.1 and 10.2. February 12, 2009 S25FL032P_00_02 S25FL032P 49 Data Sheet (Preliminary) Figure 10.1 OTP Memory Map - Part 1 ADDRESS 0x213h OT P R EGION 16 bytes (OTP16) 0x204h 0x203h 16 bytes (OTP15) 0x1F4h 0x1F3h 16 bytes (OTP14) 0x1E4h 0x1E3 16 bytes (OTP13) 0x1D4h 0x1D3h 16 bytes (OTP12) 0x1C4h 0x1C3h 16 bytes (OTP11) 0x1B4h 0x1B3h 16 bytes (OTP10) 0x1A4h 0x1A3h 16 bytes (OTP9) 0x194h 0x193h 16 bytes (OTP8) 0x184h 0x183h 16 bytes (OTP7) 0x174h 0x173h 16 bytes (OTP6) 0x164h 0x163h 16 bytes (OTP5) 0x154h 0x153h 16 bytes (OTP4) 0x144h 0x143h Address 0x112h 16 bytes (OTP3) 0x134h 0x133h 16 bytes (OTP2) 0x124h 0x123h 16 bytes (OTP1) 0x114h 0x113h 0x112h 0x111h 0x10Ah 0x109h 0x113h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 bytes (ES N2) 8 bytes (ES N1) 0x102h 0x101h 0x100h 0x100h Reserved X X X X X X Bit 1 Bit 0 B it 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2- 7 Locks R egion... OTP1 OTP2 OTP3 OTP4 OTP5 OTP6 OTP7 OTP8 OTP9 OTP10 OTP11 OTP12 OTP13 OTP14 OTP15 OTP16 ESN1 ES N2 R eserved Notes 1. Bit 0 at address 0x100h locks ESN1 region. 2. Bit 1 at address 0x100h locks ESN1 region. 3. Bits 2-7 ("X") are NOT programmable and will be ignored. 50 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Figure 10.2 OTP Memory Map - Part 2 ADDRESS 0x2FFh OT P R EGION 10 bytes (OTP31) 0x2F6h 0x2F5h 16 bytes (OTP30) 0x2E6h 0x2E5 16 bytes (OTP29) 0x2D6h 0x2D5h 16 bytes (OTP28) 0x2C6h 0x2C5h 16 bytes (OTP27) 0x2B6h 0x2B5h 16 bytes (OTP26) 0x2A6h 0x2A5h 16 bytes (OTP25) 0x296h 0x295h 16 bytes (OTP24) 0x286h 0x285h 16 bytes (OTP23) 0x276h 0x275h 16 bytes (OTP22) 0x266h 0x265h 16 bytes (OTP21) 0x256h 0x255h Address 0x214h 16 bytes (OTP20) 0x246h 0x245h 16 bytes (OTP19) 0x236h 0x235h 0x215h 16 bytes (OTP18) 0x226h 0x225h 16 bytes (OTP17) 0x216h 0x215h 0x214h X Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B it 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Locks Region... OTP17 OTP18 OTP19 OTP20 OTP21 OTP22 OTP23 OTP24 OTP25 OTP26 OTP27 OTP28 OTP29 OTP30 OTP31 R eserved Note 1. Bit 7 ("X") at address 0x215h is NOT programmable and will be ignored. February 12, 2009 S25FL032P_00_02 S25FL032P 51 Data Sheet (Preliminary) 11. Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied on VCC, and must not be driven low to select the device until VCC reaches the allowable values as follows (see Figure 11.1 and Table 11.1 on page 53): At power-up, VCC (min.) plus a period of tPU At power-down, VSS A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements. No Write Registers, program, or erase command should be sent to the device until VCC rises to the VCC min., plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power-Down mode) and the WEL bit is reset (0). Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 F), as a precaution to stabilizing the VCC feed. When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all operations are disabled and the device does not respond to any commands. Note that data corruption may result if a power-down occurs while a Write Registers, program, or erase operation is in progress. Figure 11.1 Power-Up Timing Diagram Vcc (max) Vcc Vcc (min) t PU Full Device Access Time Figure 11.2 Power-down and Voltage Drop 52 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Table 11.1 Power-Up / Power-Down Voltage and Timing Symbol VCC(min) VCC(cut-off) VCC(low) tPU TPD Parameter VCC (minimum operation voltage) VCC (Cut off where re-initialization is needed) VCC (Low voltage for initialization to occur at read/standby) VCC (Low voltage for initialization to occur at embedded) VCC(min.) to device operation VCC (low duration time) Min 2.7 2.4 1.0 2.3 300 1.0 s s Max Unit V V V 12. Initial Delivery State The device is delivered with the memory array erased i.e. all bits are set to 1 (FFh) upon initial factory shipment. The Status Register and Configuration Register contains 00h (all bits are set to 0). 13. Program Acceleration via W#/ACC Pin The program acceleration function requires applying VHH to the W#/ACC input, and then waiting a period of tWC. Minimum VHH rise and fall times is required for W#/ACC to change to VHH from VIL or VIH. Removing VHH from the W#/ACC pin returns the device to normal operation after a period of tWC. Figure 13.1 ACC Program Acceleration Timing Requirements VHH ACC VIL or VIH tVHH tVHH tWC tWC VIL or VIH Command OK Note Only Read Status Register (RDSR) and Page Program (PP) operation are allow when ACC is at (VHH). The W#/ACC pin is disabled during Quad I/O mode. Table 13.1 ACC Program Acceleration Specifications Symbol VHH tVHH tWC Parameter ACC Pin Voltage High ACC Voltage Rise and Fall time ACC at VHH and VIL or VIH to First command Min. 8.5 2.2 5 Max 9.5 Unit V ns ns February 12, 2009 S25FL032P_00_02 S25FL032P 53 Data Sheet (Preliminary) 14. Electrical Specifications 14.1 Absolute Maximum Ratings Description Ambient Storage Temperature Voltage with Respect to Ground: All Inputs and I/Os Output Short Circuit Current (Note 2) Rating -65C to +150C -0.5V to VCC+0.5V 200 mA Note 1. Minimum DC voltage on input or I/Os is -0.5V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 14.1. Maximum DC voltage on input or I/Os is VCC + 0.5V. During voltage transitions inputs or I/Os may overshoot to VCC + 2.0V for periods up to 20 ns. See Figure 14.2. 2. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 14.1 Maximum Negative Overshoot Waveform 20 ns +0.8V -0.5V -2.0V 20 ns 20 ns Figure 14.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0V VCC +0.5V 2.0V 20 ns 20 ns 15. Operating Ranges Table 15.1 Operating Ranges Description Ambient Operating Temperature (TA) Positive Power Supply Industrial Voltage Range Rating -40C to +85C 2.7V to 3.6V Note Operating ranges define those limits between which functionality of the device is guaranteed. 54 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 16. DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 17.1 on page 56, when relying on the quoted parameters. Table 16.1 DC Characteristics (CMOS Compatible) Limits Symbol VCC VHH VIL VIH VOL VOH ILI ILO Parameter Supply Voltage ACC Program Acceleration Voltage Input Low Voltage ** ** Test Conditions Min. 2.7 VCC = 2.7V to 3.6V 8.5 -0.3 0.7 x VCC IOL = 1.6 mA, VCC = VCC min. IOH = -0.1 mA VCC = VCC Max, VIN = VCC or GND VCC = VCC Max, VIN = VCC or GND At 80 MHz (Dual or Quad) At 104 MHz (Serial) At 40 MHz (Serial) VCC-0.6 Typ* Unit Max 3.6 9.5 0.3 x VCC VCC +0.5 0.4 V V V V V V 2 2 38 25 12 26 15 26 26 mA mA mA mA A A mA A A Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Output Leakage Current ICC1 Active Power Supply Current READ (SO = Open) Active Power Supply Current (Page Program) Active Power Supply Current (WRR) Active Power Supply Current (SE) Active Power Supply Current (BE) Standby Current Deep Power-down Current ICC2 ICC3 ICC4 ICC5 ISB1 IPD CS# = VCC CS# = VCC CS# = VCC CS# = VCC CS# = VCC; SO + VIN = GND or VCC CS# = VCC; SO + VIN = GND or VCC 80 3 200 10 *Typical values are at TAI = 25C and VCC = 3V Note Typical values are at TA = 25C and 3.0V. February 12, 2009 S25FL032P_00_02 S25FL032P 55 Data Sheet (Preliminary) 17. Test Conditions Figure 17.1 AC Measurements I/O Waveform 0.8 VCC Input Levels 0.2 VCC Input and Output Timing Reference levels Table 17.1 Test Specifications Symbol CL Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage Min 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC 0.5 VCC Max Unit pF ns V V V 0.7 VCC 0.5 VCC 0.3 VCC 18. AC Characteristics Figure 18.1 AC Characteristics (Sheet 1 of 2) Symbol (Notes) FSCK, R Parameter (Notes) SCK Clock Frequency for READ command SCK Clock Frequency for all others: FAST_READ(3)*, PP, QPP, P4E, P8E, SE, BE, DP, RES, WREN, WRDI, RDSR, WRR, RDID, READ_ID Clock High Time (40 MHz) Clock High Time (80 MHz) Clock High Time (104 MHz) Clock Low Time (40 MHz) Clock Low Time (80 MHz) Clock Low Time (104 MHz) Clock Rise Time (slew rate) Clock Fall Time (slew rate) CS# High Time (Read Instructions) CS# High Time (Program/Erase) CS# Active Setup Time (relative to SCK) CS# Active Hold Time (relative to SCK) Data in Setup Time Data in Hold Time Min. (Notes) DC Typ (Notes) Max (Notes) 40 104 (serial) 80 (dual/quad) Unit FSCK, C DC MHz 12.0 6.0 4.6 12.0 6.0 4.6 0.1 0.1 10 50 3 3 3 2 8 (Serial) 9.5 (Dual/Quad) V/ns V/ns ns ns ns ns ns ns ns tWH, tCH tWL, tCL tCRT, tCLCH tCFT, tCHCL tCS tCSS tCSH tSU:DAT tHD:DAT tV Clock Low to Output Valid 0 6.5 (Serial) 8 (Dual/Quad) 7 (Dual/Quad) ns tHO tDIS tHLCH Output Hold Time Output Disable Time HOLD# Active Setup Time (relative to SCK) 0 8 3 ns ns ns 56 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) Figure 18.1 AC Characteristics (Sheet 2 of 2) Symbol (Notes) tCHHH tHHCH tCHHL tHZ tLZ tWPS tWPH tW tPP tEP tSE tPE tBE tRES tDP tVHH tWC Parameter (Notes) HOLD# Active Hold Time (relative to SCK) HOLD# Non Active Setup Time (relative to SCK) HOLD# Non Active Hold Time (relative to SCK) HOLD# enable to Output Invalid HOLD# disable to Output Valid W#/ACC Setup Time (4) W#/ACC Hold Time (4) WRR Cycle Time Page Programming (1)(2) Page Programming (ACC = 9V) (1)(2)(3) Sector Erase Time (64 KB) (1)(2) Parameter Sector Erase Time (1)(2) (4 KB or 8 KB) Bulk Erase Time (1)(2) Deep Power-down to Standby Mode Time to enter Deep Power-down Mode ACC Voltage Rise and Fall time ACC at VHH and VIL or VIH to first command 2.2 5 1.5 1.2 0.5 200 32 20 100 50 3 2.4 2 800 64 30 10 Min. (Notes) 3 3 3 8 8 Typ (Notes) Max (Notes) Unit ns ns ns ns ns ns ns ms ms ms sec ms sec us us us us Notes 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern. 2. Under worst-case conditions of 85C; VCC = 2.7V; 100,000 cycles. 3. Acceleration mode (9V ACC) only in Program mode, not Erase. 4. Only applicable as a constraint for WRR instruction when SRWD is set to a `1'. Full Vcc range (2.7 - 3.6V) & CL = 30 pF Regulated Vcc range (3.0 - 3.6V) & CL = 30 pF Regulated Vcc range (3.0 - 3.6V) & CL = 15 pF 18.1 Capacitance Symbol CIN COUT Parameter Input Capacitance (applies to SCK, PO7-PO0, SI, CS#) Output Capacitance (applies to PO7-PO0, SO) Test Conditions VOUT = 0V VIN = 0V Min Max 6 8 Unit pF pF Figure 18.2 SPI Mode 0 (0,0) Input Timing CS# tCS tCSH SCK tCSS tCSH tCSS tSU:DAT tHD:DAT SI MSB IN tCRT tCFT LSB IN SO Hi-Z February 12, 2009 S25FL032P_00_02 S25FL032P 57 Data Sheet (Preliminary) Figure 18.3 SPI Mode 0 (0,0) Output Timing CS# tWH SCK tV tHO tHO LSB OUT tV tWL tDIS SO Figure 18.4 HOLD# Timing CS# tCHHL tHLCH tHHCH SCK tCHHH tHZ tLZ SO SI HOLD# Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 W# tWPS tWPH CS# SCK SI SO Hi-Z 58 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 19. Physical Dimensions 19.1 SOC008 wide -- 8-pin Plastic Small Outline Package (208-mils Body Width) 3 D A 5 4 0.20 C D A-B H SEE DETAIL B WITH PLATING 9 b1 3 E1 4 c E (b) 7 SECTION A-A 0.33 C A-B D H c1 E1/2 E/2 BASE METAL e B 5 b 0.25 M C 0.10 C q2 0.07 R MIN. GAUGE PLANE A q1 L L1 DETAIL B A q SEATING PLANE L2 A A2 0.10 C SEATING PLANE A1 C C NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N 0 5 0 MIN 0.069 0.002 0.067 0.014 0.013 0.0075 0.006 MAX 0.085 0.0098 0.075 0.019 0.018 0.0095 0.008 MIN 1.753 0.051 1.70 0.356 0.330 0.191 0.152 MAX 2.159 0.249 1.91 0.483 0.457 0.241 0.203 5. 6. 7. 8. 4. . SOC 008 (inches) SOC 008 (mm) 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 0.208 BSC 0.315 BSC 0.208 BSC .050 BSC 0.020 0.030 5.283 BSC 8.001 BSC 5.283 BSC 1.27 BSC 0.508 0.762 .055 REF .010 BSC 8 8 15 1.40 REF 0.25 BSC 8 0 5 0 8 15 9. 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 3432 \ 16-038.03 \ 10.28.04 February 12, 2009 S25FL032P_00_02 S25FL032P 59 Data Sheet (Preliminary) 19.2 SO3 016 -- 16-pin Wide Plastic Small Outline Package (300-mil Body Width) NOTES: 1. PACKAGE JEDEC SYMBOL A A1 A2 b b1 c c1 D E E1 e L L1 L2 N h 1 2 0.10 0 5 0 SO3 016 (inches) MS-013(D)AA MIN 0.093 0.004 0.081 0.012 0.011 0.008 0.008 MAX 0.104 0.012 0.104 0.020 0.019 0.013 0.012 SO3 016 (mm) MS-013(D)AA MIN 2.35 0.10 2.05 0.31 0.27 0.20 0.20 MAX 2.65 0.30 2.55 0.51 0.48 0.33 0.30 5. 6. 7. 8. 4. . 2. 3. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. DATUMS A AND B TO BE DETERMINED AT DATUM H. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE LEAD FOOT. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 3601 \ 16-038.03 \ 8.31.6 0.406 BSC 0.406 BSC 0.295 BSC .050 BSC 0.016 0.050 10.30 BSC 10.30 BSC 7.50 BSC 1.27 BSC 0.40 1.27 .055 REF .010 BSC 16 0.30 8 15 1.40 REF 0.25 BSC 16 0.25 0 5 0 0.75 8 15 9. 10. 60 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 19.3 USON 8-contact (5 x 6 mm) No-Lead Package QUAD FLAT NO LEAD PACKAGES (UNE) - PLASTIC DIMENSIONS SYMBOL e N ND L b D2 E2 D E A A1 K 0 0.45 0.00 0.55 0.35 3.90 3.30 MIN NOM 1.27 BSC 8 4 0.60 0.40 4.00 3.40 5.00 BSC 6.00 BSC 0.50 0.02 0.20 MIN. --12 2 0.55 0.05 0.65 0.45 4.10 3.50 4 3 5 MAX NOTE NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. 6. 7. 8. 9. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. PIN #1 ID ON TOP WILL BE LASER MARKED. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 3448\ 16-038.28 \ 04.19.05 February 12, 2009 S25FL032P_00_02 S25FL032P 61 Data Sheet (Preliminary) 19.4 WSON 8-contact (6 x 8 mm) No-Lead Package D N A B (DATUM A) PIN #1 ID R0.20 1 2 D2 D2/2 NX L E2/2 9. E E2 0.30 DIA TYP. 8. 2X 0.10 C 1 2X 0.10 C 0.10 C 9. 0.05 C SEATING PLANE A C 2 TOP VIEW N N-1 K NX b 4. 0.10 M C A B . e 0.05 M C . SEE DETAIL "A" e (ND-1) X 5. A1 SIDE VIEW DATUM A BOTTOM VIEW L e/2 L1 10. TERMINAL TIP e 4. DETAIL "A" NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. MAX NOTE 2. ALL DIMENSIONS ARE IN MILLIMETERS, SYM 3. N IS THE TOTAL NUMBER OF TERMINALS. 3 5 0.55 0.45 4.90 6.50 4 4. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. 6. 7. 8. 0.80 0.05 10 12 2 9. ND REFERS TOT HE NUMBER OF TERMINALS ON D SIDE. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. PIN #1 ID ON TOP WILL BE LASER MARKED. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. IS IN DEGREES. QUAD FLAT NO LEAD PACKAGES (WSNB) - PLASTIC DIMENSIONS SYMBOL e N ND L b D2 E2 D E A A1 L1 0 K 0.70 0.00 0.45 0.35 4.70 6.30 MIN NOM 1.27 BSC 8 4 0.50 0.40 4.80 6.40 6.00 BSC 8.00 BSC 0.75 0.02 0.15 MAX. --0.20 MIN. 10. A MAXIMUM 0.15 mm PULL BACK (L1) MAY BE PRESENT. 3408\ 16-038.28a 62 S25FL032P S25FL032P_00_02 February 12, 2009 Data Sheet (Preliminary) 20. Revision History Section Revision 01 (June 9, 2008) Initial release. Revision 02 (February 12, 2009) Connection Diagrams Valid Combinations Table Configuration Register Configuration Register Table Instruction Set Product Group CFI Primary Vendor-Specific Extended Query Read-ID (READ_ID) Read Status Register Read Configuration Register Parameter Sector Erase (P4E, P8E) Release from Deep Power-Down and Read Electronic Signature (RES) OTP Regions Power-up and Power-down Absolute Maximum Ratings DC Characteristics Description Added USON package. Added Tray packing type. Added OTP description for BPNV bit. Corrected TBPARM description. Added "Default" setting information upon initial factory shipment. Separated Mode bit and Dummy bytes. Corrected data of 45h bytes. Removed statement of 8-cycle buffer for Manufacturer ID and the Device ID. Corrected description for SRWD bit in the Status Register Table. Modified E_ERR and P_ERR descriptions. Updated figure. Updated figure. Updated figure. Modified description for the ACC function. Changed specification for tPU. Corrected the Table. Changed maximum specifications for ICC1 and ICC3. Modified Test Conditions for ISB1 and IPD. Changed maximum specifications for tW and tPE. AC Characteristics Changed typical time for tEP. Added note for max values assume 100k cycles. Changed Clock High/Low time. February 12, 2009 S25FL032P_00_02 S25FL032P 63 Data Sheet (Preliminary) Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2008-2009 Spansion Inc. All rights reserved. Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM, ORNAND2TM, HD-SIMTM, EcoRAMTM and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 64 S25FL032P S25FL032P_00_02 February 12, 2009 |
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